\input{../slides/slides_common}

\newif\ifbook
\input{../shared/chisel}

\title{Chisel: Software Defined Hardware}
\subtitle{Digital Design in the 21st Century}
\author{Martin Schoeberl\\
\url{mailto:masca@dtu.dk}}
\date{\today}
\institute{Technical University of Denmark}

\begin{document}

\begin{frame}
\titlepage
\end{frame}

\begin{frame}[fragile]{Motivating Example:\\
Lipsi: Probably the Smallest Processor in the World}
\begin{itemize}
\item Tiny processor
\item Simple instruction set
\item Shall be small
\begin{itemize}
\item Around 200 logic cells, one FPGA memory block
\end{itemize}
\item Hardware described in Chisel
\item Available at \url{https://github.com/schoeberl/lipsi}
\item Usage
\begin{itemize}
\item Utility processor for small stuff
% \item Could be used for your vending machine
\item In teaching for introduction to computer architecture
\end{itemize}
\item The design took place on the island Lipsi
\end{itemize}
\end{frame}

\begin{frame}[fragile]{The Design of Lipsi on Lipsi}
\begin{figure}
    \centering
    \includegraphics[scale=0.3]{lipsi}
\end{figure}
\end{frame}

\begin{frame}[fragile]{Lipsi Implementation}
\begin{itemize}
\item Hardware described in Chisel
\item Tester in Chisel
\item Assembler in Scala
\begin{itemize}
\item Core case statement about 20 lines
\end{itemize}
\item Reference design of Lipsi as software simulator in Scala
\item Testing:
\begin{itemize}
\item Self testing assembler programs
\item Comparing hardware with a software simulator
\end{itemize}
\item All in a single programming language!
\item All in a single program
\item How much work is this?
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel is Productive}
\begin{itemize}
\item All coded and tested in less than 14 hours!
\end{itemize}
\begin{itemize}
\item The hardware in Chisel
\item Assembler in Scala
\item Some assembler programs (blinking LED)
\item Simulation in Scala
\item Two testers
\end{itemize}
\begin{itemize}
\item BUT, this does not include the design (done on paper)
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Motivating Example: Lipsi, a Tiny Processor}
\begin{itemize}
\item Show in IntelliJ
\end{itemize}
\end{frame}

%\begin{frame}[fragile]{The Slides are Online}
%\begin{itemize}
%\item \url{https://github.com/schoeberl/chisel-book/wiki}
%\end{itemize}
%\begin{figure}
%    \centering
%    \includegraphics[scale=0.5]{slides-link}
%\end{figure}
%\end{frame}

\begin{frame}[fragile]{More on Chisel Success Stories}
\begin{itemize}
\item CCC 2020 (in silicon valley)
\item 90 participants
\item More than 30 different (hardware) companies present
\item Several companies are looking into Chisel
\item IBM did an open-source PowerPC
\item \href{https://www.sifive.com/}{SiFive} is a RISC-V startup success
\begin{itemize}
\item High productivity with Chisel
\item Open-source Rocket chip
\end{itemize}
\item Esperanto uses the BOOM processor in Chisel
\item Google did a machine learning processor
\item Intel is looking at Chisel
\item Chisel is open-source, if there is a bug you can fix it
\begin{itemize}
\item You can contribute to the Chisel ecosystem
\end{itemize}
\end{itemize}
\end{frame}

%\begin{frame}[fragile]{Goals for this Intro}
%\begin{itemize}
%\item Get an idea what Chisel is
%\begin{itemize}
%\item Will show you code snippets
%\end{itemize}
%\item A first high level view of the main features of Chisel
%\item Reconsider how to describe hardware
%\item Some experience report from usage at DTU
%\item Pointers to more information
%\end{itemize}
%\end{frame}

%\begin{frame}[fragile]{Talk abstract}
%
%Date: Tu 19/04/2016, 11:00-12:00
%Room: 123/322
%
%Title: Hardware Design in the 21st Century: with the Object Oriented
%and Functional Language Chisel
%
%Chisel is a hardware construction language implemented as a
%domain specific language in Scala. Therefore, the full power of
%a modern programming language is available to describe hardware
%and, more important, hardware generators. Chisel has been developed
%at UC Berkeley and successfully used for several tape outs of RISC-V.
%Here at DTU we used Chisel in the T-CREST project and in teaching
%advanced computer architecture. Besides presenting small code
%examples in Chisel I will report on experiences on using Chisel in
%the t-CREST project and in teaching.
%
%Martin Schoeberl
%\end{frame}

\begin{frame}[fragile]{Chisel}
\begin{itemize}
\item A hardware \emph{construction} language
\begin{itemize}
\item Constructing Hardware In a Scala Embedded Language
\item If it compiles, it is synthesysable hardware 
\item Say goodby to your unintended latches
\end{itemize}
\item Chisel is not a high-level synthesis language
\item Single source two targets
\begin{itemize}
\item Cycle accurate simulation (testing)
\item Verilog for synthesis
\end{itemize}
\item Embedded in Scala
\begin{itemize}
\item Full power of Scala available
\item But to start with, no Scala knowledge needed
\end{itemize}
\item Developed at UC Berkeley
\end{itemize}
\end{frame}

\begin{frame}[fragile]{The C Language Family}

\Tree[.C [
   [.{\bf Verilog} {\bf SystemVerilog} ]
   [.C++  \emph{SystemC}  ]
   [.Java [.Scala {\bf Chisel} ] ]
   [.C\# ] ] ]
 
\end{frame}

\begin{frame}[fragile]{Other Language Families}

\begin{columns}
\column{0.5\textwidth}
\begin{center}
\Tree[.Algol [.Ada [.{\bf VHDL} ] ] ]
\end{center}
\column{0.5\textwidth}
\begin{center}
\Tree[.Python [.{\bf MyHDL} ] ]
\end{center}
\end{columns}
\end{frame}

\begin{frame}[fragile]{Some Notes on Scala}
\begin{itemize}
\item Object oriented
\item Functional
\item Strongly typed
\begin{itemize}
\item With very good type inference
\end{itemize}
\item Could be seen as Java++
\item Compiled to the JVM
\item Good Java interoperability
\begin{itemize}
\item Many libraries available
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel vs. Scala}
\begin{itemize}
\item A Chisel hardware description is a Scala program
\item Chisel is a Scala library
\item When the program is executed it generates hardware
\item Chisel is a so-called \emph{embedded domain-specific language}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{A Small Language}
\begin{itemize}
\item Chisel is a \emph{small} language
\item On purpose
\item Not many constructs to remember
\item The \href{https://github.com/freechipsproject/chisel-cheatsheet/releases/latest/download/chisel_cheatsheet.pdf}{Chisel Cheatsheet} fits on two pages
\item The power comes with Scala for circuit generators
\item With Scala, Chisel can grow with you
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Tool Flow for Chisel}
\begin{figure}
    \centering
    \includegraphics[scale=0.35]{../figures/flow}
\end{figure}
\end{frame}

\begin{frame}[fragile]{Expressions are Combinational Circuits}
\begin{chisel}
(a | b) & ~(c ^ d)

val addVal = a + b
val orVal = a | b
val boolVal = a >= b
\end{chisel}
\begin{itemize}
\item The usual operations 
\item Simple name assignment with val
\item Width inference
\item Type inference
\item Types: Bits, UInt, SInt, Bool
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Conditional Updates for Combinational Circuits}
\shortlist{../code/comb_elsewhen.txt}
\begin{itemize}
\item Similar to VHDL \code{process} or SystemVerilog \code{always\_comb}
\item Chisel checks for complete assignments in all branches
\item Latches give compile error
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Registers}
\begin{chisel}
val cntReg = RegInit(0.U(32.W))

cntReg := cntReg + 1.U
\end{chisel}
\begin{itemize}
\item Type inferred by initial value (= reset value)
\item No need to specify a clock or reset signal
\end{itemize}
\begin{itemize}
\item Also definition with an input signal connected:
\end{itemize}
\begin{chisel}
val r = RegNext(nextVal) 
\end{chisel}
\end{frame}

\begin{frame}[fragile]{Functional Abstraction}
\begin{chisel}
  def addSub(add: Bool, a: UInt, b: UInt) =
    Mux(add, a+b, a-b)

  val res = addSub(cond, a, b)
  
  def rising(d: Bool) = d && !RegNext(d)
\end{chisel}
\begin{itemize}
\item Functions for repeated pieces of logic
\item May contain state
\item Functions may return \emph{hardware}
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Bundles}
\begin{chisel}
class DecodeExecute extends Bundle {
  val rs1 = UInt(32.W)
  val rs2 = UInt(32.W)
  val immVal = UInt(32.W)
  val aluOp = new AluOp()
}
\end{chisel}
\begin{itemize}
\item Collection of values in named fields 
\item Like struct or record
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Vectors}
\begin{chisel}
val myVec = Vec(3, SInt(10.W))

myVec(0) := -3.S
val y = myVec(2)
\end{chisel}
\begin{itemize}
\item Indexable vector of elements
\item Bundles and Vecs can be arbitrarely nested
\end{itemize}
\end{frame}

\begin{frame}[fragile]{IO Ports}
\begin{chisel}
class Channel extends Bundle {
  val data = Input(UInt(8.W))
  val ready = Output(Bool())
  val valid = Input(Bool())
}
\end{chisel}
\begin{itemize}
\item Ports are Bundles with directions
\item Direction can also be assigned at instantiation:
\end{itemize}
\begin{chisel}
class ExecuteIO extends Bundle {
  val dec = Input(new DecodeExecute())
  val mem = Output(new ExecuteMemory())
}
\end{chisel}
\end{frame}

%\begin{frame}[fragile]{Modules}
%\begin{chisel}
%class Adder extends Module {
%  val io = IO(new Bundle {
%    val a = Input(UInt(4.W))
%    val b = Input(UInt(4.W))
%    val result = Output(UInt(4.W))
%  })
%
%  val addVal = io.a + io.b
%  io.result := addVal
%}
%\end{chisel}
%\begin{itemize}
%\item Organization of components
%\item IO ports defined as a Bundle named \code{io} and wrapped into an \code{IO()}
%\item Created (instantiated) with:
%\end{itemize}
%\begin{chisel}
%val adder = Module(new Adder())
%\end{chisel}
%\end{frame}

\begin{frame}[fragile]{Hello World in Chisel}
\shortlist{../code/hello.txt}
\end{frame}

\begin{frame}[fragile]{Connections}
\begin{itemize}
\item Simple connections just with assignments, e.g.,
\begin{chisel}
  adder.io.a := ina
  adder.io.b := inb
\end{chisel}
\item Automatic bulk connections between components
\begin{chisel}
  dec.io <> exe.io
  mem.io <> exe.io
\end{chisel}
\end{itemize}
\end{frame}

\input{generation.tex}

%\begin{frame}[fragile]{Testing}
%\begin{chisel}
%class CounterTester(c: Counter) extends PeekPokeTester(c) {
%  for (i <- 0 until 5) {
%    println(i.toString + ": " + peek(c.io.out).toString())
%    step(1)
%  }
%}
%\end{chisel}
%\begin{itemize}
%\item Within Chisel with a tester (= Scala program)
%\item May include waveform generation
%\item peek and poke to read and set values
%\begin{itemize}
%\item Remember the BASIC days ;-)
%\end{itemize}
%\item printf in simulation on rising edge
%\begin{chisel}
%printf("Counting %x\n", r1)
%\end{chisel}
%\end{itemize}
%\end{frame}

%\begin{frame}[fragile]{Conditional Component Generation}
%\begin{chisel}
%val icache =
%  if (TYPE == METHOD)
%    Module(new MCache())
%  else if (TYPE == LINE)
%    Module(new ICache())
%  else
%    ChiselError.error("Unsupported Type")
%\end{chisel}
%\begin{itemize}
%\item Use Scala if/else for conditional component types
%\item Code example from Patmos
%\item We parse an XML file for the configuration
%\end{itemize}
%\end{frame}




\begin{frame}[fragile]{Free Tools for Chisel and FPGA Design}
\begin{itemize}
\item \href{https://adoptopenjdk.net/}{Java OpenJDK 8}
\item \href{https://www.scala-sbt.org/}{sbt, the Scala (and Java) build tool}
\item \href{https://www.jetbrains.com/idea/download/}{IntelliJ (the free Community version)}
\item \href{http://gtkwave.sourceforge.net/}{GTKWave}
\item \href{https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html}{Vivado WebPACK} or
\item \href{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}{Quartus}
\item Nice to have:
\begin{itemize}
\item make, git
\end{itemize}
\end{itemize}
\end{frame}


%\begin{frame}[fragile]{An IDE for Chisel}
%\begin{itemize}
%\item IntelliJ
%\item Scala plugin
%\item For IntelliJ: File - New - Project from Existing Sources..., open build.sbt
%%\item But you are not compiling with Eclipse\\ and against the Chisel source
%\end{itemize}
%\end{frame}

\begin{frame}[fragile]{Chisel in the T-CREST Project}
\begin{itemize}
\item Patmos processor rewritten in Chisel
\begin{itemize}
\item As part of learning Chisel
\item 6.4.2013: Chisel: 996 LoC vs VHDL: 3020 LoC
\item But VHDL was very verbose, with records maybe 2000 LoC
\end{itemize}
\item Memory controller, memory arbiters, IO devices in Chisel
\item Several Phd, master, and bachelor projects:
\begin{itemize}
\item Patmos stack cache
\item Method cache for Patmos
\item TDM based memory arbiter
\item RISC stack cache
\item and some more
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel in Teaching}
\begin{itemize}
\item Using/offering it in Advanced Computer Architecture
\item Spring 2016--2018 all projects have been in Chisel
\item Several Bachelor and Master projects
\item Students pick it up reasonable fast
\item For software engineering students easier than VHDL
\item Switched Digital Electronics 2 at DTU to Chisel (spring semester 2020)
\item Issue of \emph{writing a program} instead of describing hardware remains
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel in Digital Electronic 2}
\begin{itemize}
\item Basic RTL level digital design wit Chisel
\item Chisel testers for debugging
\item Very FPGA centric course
\item Final project is a vending machine
\item All material (slides, book, lab material) in open source
\item Tried to coordinate with introduction to programming (Java)
\begin{itemize}
\item But sometimes I was ahead with Chisel constructs (e.g., classes)
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Then there was the Lockdown}
\begin{itemize}
\item Usually one FPGA board per group
\item No group meetings
\item Just virtual labs
\item Can I do something about it with Chisel?
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Teaching Feedback}
\begin{itemize}
\item General positive feedback of the course
\item Most students liked Chisel
\item They also liked the (free) Chisel book
\item Better link to Java programming (same JVM)
\begin{itemize}
\item Similar setup (IDE)
\end{itemize}
\item Lab finish about the same time as last year with VHDL
\begin{itemize}
\item So Chisel is not more productive than VHDL?
\item But we had the Corona lockdown
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{A Chisel Book}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../cover-small}
\end{figure}

\begin{itemize}
\item Available in open access (PDF)
\item In paper from Amazon
\item see \url{http://www.imm.dtu.dk/~masca/chisel-book.html}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{What May Happen with an Open-Source Book}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../cover-small-chinese}
\end{figure}

\begin{itemize}
\item A free Chinese translation
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Furthermore, I got This}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../japanese}
\end{figure}

\begin{itemize}
\item A Japanese translation
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Further Information}
\begin{itemize}
\item \url{https://www.chisel-lang.org/}
\item \url{http://www.imm.dtu.dk/~masca/chisel-book.html}
\item \url{https://github.com/ucb-bar/chisel-tutorial}
\item \url{https://github.com/ucb-bar/generator-bootcamp}
%\item Chisel 2 documentation at \url{https://github.com/schoeberl/chisel2-doc}
%\begin{itemize}
%\item Chisel 2.2 Tutorial
%\item Getting Started with Chisel
%\end{itemize}
\item \url{http://groups.google.com/group/chisel-users}
\item \url{https://github.com/schoeberl/chisel-book}
\item \url{https://github.com/schoeberl/chisel-lab}
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Summary}
\begin{itemize}
\item Processors do not get much faster -- we need to design custom hardware
\item We need a modern language for hardware/systems design
\item Chisel is a small language
\item Embedding it in Scala gives the power
\item We can write circuit generators
\item We can do co-simulation
% \item You can get started with a hardware design in a special course or 4th semester project
\item I can provide further introduction into Chisel including labs
\end{itemize}
\end{frame}

\end{document}

\begin{frame}[fragile]{Title}
\begin{itemize}
\item abc
\end{itemize}
\end{frame}
